Non-volatile memory (NVM) systems including arrays of NVM cells are used in a variety of electronic systems and devices. During the operation of an NVM system, NVM cells are often erased using an embedded erase process that includes a number of steps. Certain events during embedded erase operations, such as brown-out events and/or cells that are slow to erase, can leave a portion of the NVM cells in charge states that can cause problems in subsequent operations for the NVM system.
FIG. 1 (Prior Art) is a flow diagram of an embodiment 100 for an embedded erase operation for NVM cells within an NVM array for an NVM system. The embedded erase operation starts in block 102 and proceeds to block 104 where a determination is made whether column leakage currents for the NVM array are below a predetermined threshold. If “NO,” then flow passes directly to erase verify determination block 110. If “YES,” then flow passes to block 106 where a program verify determination is made. The program verify determination in block 106 determines whether the threshold voltage levels for the NVM cells exceed a program verify voltage level. If “YES,” then flow passes to block 110. If “NO,” then flow passes to block 108 where a pre-program pulse is applied to the NVM cells that failed program verify. The pre-program pulse adds charge to the charge storage layers within the NVM cells. Flow then passes to block 110, or if desired, flow can pass back to determination block 106 wherein a program verify determination is again made. Once determination block 110 is reached, an erase verify determination is performed. The erase verify determination in block 110 determines whether the threshold voltage levels for the NVM cells fall below an erase verify voltage level. If “YES,” then flow passes to determination block 114. If “NO,” then flow passes to erase block 112 where an erase pulse is applied to all the NVM cells in the array. The erase pulse removes charge from the charge storage layers within the NVM cells. Flow then passes back to determination block 110 wherein an erase verify determination is again made. Once determination block 114 is reached, a soft program verify operation is performed. The soft program verify determination in block 114 determines whether the threshold voltage levels for the NVM cells exceed a soft program verify voltage level. If “NO,” then flow passes to soft program block 116 where a soft program pulse is applied to the NVM cells that failed soft program verify. The soft program pulse adds charge to the charge storage layers within the NVM cells using weaker bias voltage than program pulse. Flow then passes back to determination block 114 wherein a soft program verify determination is again made. Once all cells pass the soft program verify in determination block 114 and the determination is “YES,” then flow passes to block 118 where the embedded erase process finishes.
For the embedded erase embodiment 100, therefore, after all the cells pass erase verify in block 114, soft program pulses will be applied in block 116 if any of the cells fall below the soft program verify voltage. If any cell then still fails soft program verify in block 114, soft program pulses will again be applied to the failing cells in block 116, and this will continue until all cells pass soft program verify in block 114. Once all cells pass, embedded erase is done and block 118 is reached. In some cases, however, a large number of soft program pulses may be required before block 118 is reached. For example, a large number of over-erased cells can exist that require extensive soft program pulses before all cells are recovered and pass the soft program verify determination in block 114. A large number of over-erased cells can occur, for example, when embedded erase operations are interrupted (e.g., by a brown-out) before the soft program operation in blocks 114 and 116 completes. Further, a large number of over-erased cells can be generated where intermittent slow erase cells lead to a large number of additional erase pulses being applied to the NVM cells before all cells will pass the erase verify determination in block 110. Using large numbers of soft programming pulses to satisfy soft programming verify in block 114, however, can lead to disturbed or over-soft-programmed cells that have threshold voltage levels that significantly exceed the erase verify level and hence have less normal read margin. Such disturbed or over-soft-programmed cells can lead to latent read failures and induce potential reliability issues.
FIG. 2 (Prior Art) is a probability distribution diagram of an embodiment 200 for threshold voltages of the NVM cells having a large number of over-erased cells. The x-axis 204 represents threshold voltage (Vt), and the y-axis 202 represents numbers of cells at the threshold voltage levels. Curve 214 represents a probability distribution curve for cells within an NVM cell array where a large portion 216 of the cells are over-erased and have threshold voltages that fall below the soft program verify voltage (VSPV) level 206. It is noted that voltage level 206 represents a soft-program verify voltage (VSPV) level used during soft-program verify operations. Voltage level 208 represents an erase verify voltage (VEV) level used during erase verify operations. Voltage level 212 represents a program verify voltage (VPV) level used during pre-program verify operations. And voltage level 210 represents a read voltage level (VR) used during read operations. For read operations, if the threshold voltage level of the accessed cell is above the read gate bias voltage (VR) 210, the NVM cell is determined to be programmed (e.g., logic 0). If the threshold voltage level of the accessed cell is below the read gate bias voltage (VR) 210, the NVM cell is determined to be erased (e.g., logic 1).
FIG. 3 (Prior Art) is a probability distribution diagram of an embodiment 300 for threshold voltages of the NVM cells having disturbed or over-soft-programmed cells after soft program operation has been performed on the cell distribution of embodiment 200. In particular, as shown in embodiment 300, soft program operations have adjusted the threshold voltages for the NVM cells such that the prior distribution curve 214 has been adjusted to new distribution curve 302. All of the cells now have threshold voltage levels that exceed the soft program verify voltage (VSPV) level 206. As such, the cells will pass soft program verify in determination block 114 described above. However, as also described above, when a large number of soft program pulses are utilized to move the voltage distribution curve 214 so that all cells will rise above the soft program verify voltage (VSPV) level 206, a number of disturbed or over-soft-programmed cells 304 can be generated that have threshold voltages that exceed the erase verify voltage (VEV) level 208. These cells with elevated threshold voltages above the erase verify voltage (VEV) level decrease read margin and induce potential read failures. Further, some of these disturbed or over-soft-programmed cells 304 can also have threshold voltages that extend above the read voltage (VR) level 210 thus induce read error, as well.